Power-on reset circuit based upon FET threshold level

Details Power-on reset circuit based upon FET threshold level Power-on reset circuit based upon FET threshold level

1997-03-25

1999-03-16

Ton, My-Trang Nu

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327198, H03L 700, H03K 302

Patent

active

058835326

ABSTRACT:
A power-on reset circuit initiates a reset signal when the circuit's power supply voltage is low, and terminates the signal in response to the supply voltage exceeding a reset termination threshold that is based upon the greater of the threshold voltages for p-channel and n-channel FETs employed in the circuit. The reset termination threshold is preferably the sum of the greater FET threshold plus a safety margin, with the termination delayed by a predetermined period to ensure an adequate reset period, and a hysteresis feature added to ensure a stable reset termination.

REFERENCES:
patent: 4754166 (1988-06-01), Nagano
patent: 5039875 (1991-08-01), Chang
patent: 5349244 (1994-09-01), Confalonieri
patent: 5602502 (1997-02-01), Jiang
Paul Horowitz, Winfield Hill, The Art of Electronics, Cambridge University Press, New York, 1989, pp. 614-616.

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