Method and apparatus for testing high pin count integrated circu

Details Method and apparatus for testing high pin count integrated circu Method and apparatus for testing high pin count integrated circu

1989-03-24

1991-01-29

Smith, Jerry

Excavating

371 251, 371 27, G06F 1100

Patent

active

049892096

ABSTRACT:
An interface apparatus for coupling a multi-channel tester to a high pin count logic circuit for use in testing the logic circuit is provided wherein a plurality of terminal electronics units are coupled to each test channel of the multi-channel tester. Some of the terminal electronics units are coupled to each other in parallel by at least one stimulus shift register, which serves to divide a serial stimulus vector among the terminal electronics units, and one response shift register, which serve to assembly the response data from several terminal electronics units into a serial response vector. The serial stimulus vector is generated, and the serial response vector is analyzed by the multi-channel tester. The apparatus is capable of operating in one of a plurality of modes used for functional testing, parametric testing, and high speed scan path testing of the logic circuit.

REFERENCES:
patent: 4287594 (1981-09-01), Shirasaka
patent: 4348759 (1982-09-01), Schnurmann
patent: 4517661 (1985-05-01), Graf
patent: 4566104 (1986-01-01), Bradshaw
patent: 4571724 (1986-02-01), Belmondo
M. Markowitz, "High-Density IC's Need Design-for-Test Methods", Electronic Design News, 11/1988, pp. 73-86.

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