MOS transistor read-only memory device

Details MOS transistor read-only memory device MOS transistor read-only memory device

1998-06-22

1999-03-16

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

257390, 257391, 257400, 257758, 257903, H01L 2711

Patent

active

058834052

ABSTRACT:
A MOS semiconductor ROM device is provided which is capable of preventing an ion implantation region of one memory cell from overlapping into a region of an adjacent memory cell and causing a threshold voltage V.sub.T of the adjacent memory cell from rising. The device contains a semiconductor substrate, first and second linear regions, first and second interconnect lines, a first notch, and a first doping area. The first linear region is formed over the semiconductor substrate, and the second linear region is formed over the semiconductor substrate parallel to the first linear region. The first interconnect line is formed over the semiconductor substrate and is perpendicular to the first and second linear regions, and the second interconnect line is formed over the substrate parallel to the first interconnect line. The first notch is formed in the first interconnect line between the first and second linear regions to form a narrowed portion of the first interconnect line. The first doping area is defined between the first and second linear regions and below the narrowed portion of the first interconnect line and is doped with impurities.

REFERENCES:
patent: 5027175 (1991-06-01), Iwasa
patent: 5031018 (1991-07-01), Shirato et al.
patent: 5172198 (1992-12-01), Aritome et al.
patent: 5204542 (1993-04-01), Namiki et al.
patent: 5608241 (1997-03-01), Shibuya et al.
patent: 5691551 (1997-11-01), Eimori
patent: 5760452 (1998-06-01), Terada
patent: 5811862 (1998-09-01), Okugaki et al.

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