Multiple error trapping

Details Multiple error trapping Multiple error trapping

1987-12-17

1989-06-27

Smith, Jerry

Excavating

G06F 1110

Patent

active

048436070

ABSTRACT:
By translating in accordance with a predetermined permutation the virtual check locations of a virtual message re-encoder, plural erroneous symbols (up to a certain limit) occurring in any pattern in a received codeword may be trapped simultaneously in virtual check locations. By simply adding to them the corresponding virtual check symbols computed by the virtual message re-encoder, the correct codeword is easily obtained. In one embodiment of the invention, any pattern of two erroneous symbols in a codeword of length n may be trapped in this manner by defining the predetermined permutation in accordance with a modulus n cyclic difference set. In this embodiment, for an RS(31, 25) code, the cyclic difference set (0, 4, 10, 23, 24, 26) may be used as the predetermined permutation.

REFERENCES:
patent: 4414667 (1983-11-01), Bennett
patent: 4566105 (1986-01-01), Oisel
patent: 4584686 (1986-04-01), Fritze

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