Semiconductor memory device with address transition detection an

Details Semiconductor memory device with address transition detection an Semiconductor memory device with address transition detection an

Filed on

1987-11-24

Date issued

1989-06-27

Examiner

Fears, Terrell W.

Patent Class

Static information storage and retrieval

SubClass

Addressing

SubSubClass

Sync/clocking

Other Related Categories

36518908, G11C 800

Type

Patent

Status

active

Patent number

048435961

Description

ABSTRACT:
A novel semiconductor memory device includes an address detection circuit that produces a short-width pulse in response to the detection of an address change. A column decoder-activating signal generator detects the start of the short-width pulse and in response generates a column decoder-activating signal. A second detection circuit detects the conclusion of the short-width pulse and generates a second pulse that triggers a preamplifier-activating signal that activates a preamplifier and latches the data that is present on the input/output line. A reset signal generator produces a reset signal to deactivate the column decoder-activating signal and to delay the preamplifier-activating signal. The preamplifier-activating signal generator and the reset signal generator are reset while the first pulse is output.

REFERENCES:
patent: 4272832 (1981-06-01), Ito
patent: 4337525 (1982-06-01), Akatsuka
patent: 4558435 (1985-12-01), Hsieh
patent: 4656612 (1987-04-01), Allan
patent: 4739502 (1988-04-01), Nozaki
"Development Technique and Further Development of Hitachi Mega-Bit DRAM", Katsuyuki Sato (Hitachi), May 22-23, 1985.

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