Pipelineable structure for efficient multiplication and accumula

Details Pipelineable structure for efficient multiplication and accumula Pipelineable structure for efficient multiplication and accumula

1987-09-14

1989-06-27

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 752

Patent

active

048435856

ABSTRACT:
A pipelineable multiplier which implements two's complement Modifiied Booths' algorithm multiplication. Partial product bits are formed to create an array having an integer number of rows and columns. An addition of partial product bits of each row is accomplished in pipelined fashion by using an arithmetic machine for each row. Each arithmetic machine is a time multiplexed summer including a plurality of full adders, the number of full adders being proportional to a ratio of the sum and carry bit propagation delays of each of the full adders. In one form, full adders having a carry propagation delay substantially twice as fast as a sum propagation delay are used in the pipelineable structure.

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