Hybrid wafer scale microcircuit integration

Details Hybrid wafer scale microcircuit integration Hybrid wafer scale microcircuit integration

1990-04-24

1991-01-29

Carroll, J.

357 40, 357 49, 357 55, 357 72, 357 75, H01L 2702, H01L 2722, H01L 2934, H01L 2906

Patent

active

049890638

ABSTRACT:
A wafer scale integration arrangement wherein integrated circuit die of varying size, fabrication processes, and function are commonly mounted in the same host wafer using a filled epoxy material of special characteristics. The mounting epoxy material also serves as a substrate for the die interconnecting conductors in regions adjacent the mounted die. The described assembly also includes a newly available photosensitive polyimide material as a planarization and passivation covering for the die and host wafer and as a mounting surface for an interconnecting metal conductor array. Multiple levels of interconnection metal. Fabrication processes for the die to host wafer attachment and the passivation covering of the assembly are disclosed.

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