Multiple-input binary adder

Details Multiple-input binary adder Multiple-input binary adder

1981-03-19

1983-08-16

Malzahn, David H.

Boots, shoes, and leggings

364786, G06F 750

Patent

active

043995179

ABSTRACT:
An improved 6-input adder is disclosed. The adder decodes pairs of inputs to provide three sets of NAND, NOR and Exclusive OR terms which are inputted to AND-OR-INVERT arrays which generate first and second carry output terms of a 3-bit binary number in less than three gate delays.

REFERENCES:
patent: 3515344 (1970-06-01), Goldschmidt et al.
patent: 3535502 (1970-10-01), Clapper
patent: 3603776 (1971-09-01), Weinberger
patent: 3636334 (1972-01-01), Svoboda
patent: 3675001 (1972-07-01), Singh
patent: 3711692 (1973-01-01), Batcher
patent: 3723715 (1973-03-01), Chen et al.
Singh, "Fast Adder for Multinumber Addition", IBM Tech. Disclosure Bulletin, vol. 15, No. 9, Feb. 1973, pp. 2939-2940.
Kobayashi et al., "A Synthesis Method for Multiple Input Adders with a ROM Network", Systems-Computers-Controls, vol. 10, No. 1, 1979, pp. 9-16.

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