Non-volatile semiconductor memory device using contact hole conn

Details Non-volatile semiconductor memory device using contact hole conn Non-volatile semiconductor memory device using contact hole conn

1989-04-17

1991-01-29

Mintel, William

357 45, 357 53, H01L 2978

Patent

active

049890549

ABSTRACT:
First, second, third and fourth impurity regions are formed on a major surface of a semiconductor substrate with prescribed spaces, to define first, second and third channel regions in portions held between the same. A select gate is formed on the first channel region through an insulating film, to define a transistor with the first and second impurity regions. A part of a control gate is formed on the third channel region through an insulating film, to define a transistor with the third and fourth impurity regions. A floating gate is formed on the second channel region and parts of the select gate and the control gate through an insulating film, to define a transistor with the second and third impurity regions. Both end portions of the floating gate are inwardly separated from upper positions of respective outer ends of parts of the select gate and the control gate, in order to improve an effect of shielding the floating gate against a fourth impurity region. Another part of the control gate is formed on the floating gate through an insulating film. The first impurity region is connected to a bit line and the fourth impurity region is connected to a source region respectively.

REFERENCES:
patent: 4417264 (1983-11-01), Angle
patent: 4455742 (1984-08-01), Williams et al.
patent: 4513397 (1985-04-01), Ipri et al.
patent: 4907198 (1990-03-01), Arima
J. Yeargain and C. Kuo "A High Density Floating EEPROM Cell", IEDM 81 (1981), pp. 24-27.
Z. Einberg "On Tunneling in Metal-Oxide Silicon Structures", Journal of Applied Physics 57(7), Jul. 1982, pp. 5052-5056.

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