Method for fabricating MOS transistors having gates with differe

Details Method for fabricating MOS transistors having gates with differe Method for fabricating MOS transistors having gates with differe

1987-03-30

1987-12-22

Powell, William A.

Fishing, trapping, and vermin destroying

437 44, 156648, 156653, 156657, 156662, H01L 21306, B44C 122, C03C 1500, C03C 2506

Patent

active

047145196

ABSTRACT:
A process for forming an insulated gate field effect transistor (IGFET) having a semiconductor gate with a central portion and end portions on either side thereof where the portions are of two different conductivity types. Typically, a central portion of the gate, such as a doped polysilicon portion of a first conductivity type, is flanked by end portions near the source/drain regions, where the end portions are doped with an impurity of a second conductivity type. The central portion of the gate is formed by conventional gate patterning whereas the end portions are formed by typical procedures for forming sidewall spacers using a conformal layer of in situ doped polycrystalline silicon (polysilicon) or other semiconductor material and an anisotropic etch.

REFERENCES:
patent: 4559694 (1985-12-01), Yoh et al.
patent: 4577391 (1986-03-01), Hsia et al.
patent: 4597824 (1986-07-01), Shinada et al.
patent: 4678537 (1987-07-01), Ohuchi

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