Method of planarization using interlayer dielectric

Details Method of planarization using interlayer dielectric Method of planarization using interlayer dielectric

1997-08-25

1999-03-16

Powell, William

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

216 38, 438697, H01L 2100

Patent

active

058830049

ABSTRACT:
A method for planarizing interlayer dielectric is disclosed. The present invention includes firstly forming a barrier layer over a semiconductor substrate. Next, a buffer layer is formed on the barrier layer by a spin-on-glass technique. A dielectric layer is formed on the buffer layer, wherein etch rate of the dielectric layer is larger than etch rate of the buffer layer, and the barrier layer serves as a block of autodoping coming from the dielectric layer. Finally, the dielectric layer is etched back using the buffer layer as buffer, thereby planarizing the dielectric layer.

REFERENCES:
patent: 5250472 (1993-10-01), Chen et al.
patent: 5674783 (1997-10-01), Jang et al.
patent: 5674784 (1997-10-01), Jang et al.
patent: 5700349 (1997-12-01), Tsukamoto et al.

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