High speed CMOS latch without pass-gates

Details High speed CMOS latch without pass-gates High speed CMOS latch without pass-gates

1989-07-31

1991-01-29

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307279, 307481, 307290, 377117, H03K 3037, H03K 3356, H03K 19069, H03K 17687

Patent

active

049888960

ABSTRACT:
A high performance latch circuit having complemented isolation means that selectively maintain the state of the latch at a given logic state or input a new logic state thereto. The latch is made up of several legs of series connected translators, the legs being connected in parallel. Selective gating is provided by the transistors directly coupled to the output node.

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IBM Technical Disclosure Bulletin, vol. 16, No. 7, Dec. 1973.
IBM Technical Disclosure Bulletin, vol. 27, No. 1B, Jun. 1984.
IBM Technical Disclosure Bulletin, vol. 27, No. 7B, Dec. 1984.
IBM Technical Disclosure Bulletin, vol. 27, No. 10B, Mar. 1985.

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