Temperature compensated monolithic delay circuit

Details Temperature compensated monolithic delay circuit Temperature compensated monolithic delay circuit

1988-06-30

1989-06-27

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307228, 307246, 307310, 307594, 3072966, 323907, G05F 1567

Patent

active

048432652

ABSTRACT:
A temperature and processing compensated time delay circuit of the type which can be fabricated in a monolithic integrated circuit utilizes a field effect transistor (FET) (12) connected to the terminals of a charged capacitor (14). A bias voltage connected to the gate of the FET (12) varies with temperature in a manner to compensate for the changes in current which flows from the capacitor (14) through the FET (12) due to changes in temperature. The bias voltage also varies from one integrated circuit to another in a manner to compensate for variations in FET threshold voltage caused by variations in the processing of the integrated circuits.

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Broit, "Linear Voltage Regulation Versus Temperature", IBM T.D.B., vol. 13, No. 5, pp. 1253-1254.

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