Low capacitance interconnect structures in integrated circuits u

Details Low capacitance interconnect structures in integrated circuits u Low capacitance interconnect structures in integrated circuits u

1997-03-21

1998-10-06

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

257758, 257775, 257748, 438631, H01L 2348, H01L 2952, H01L 2940

Patent

active

058181113

ABSTRACT:
An improved method and structure is provided for integrating HSQ and other low dielectric constant materials, which may have undesirable properties, into integrated circuit structures and processes, especially those requiring multiple levels of interconnect lines. The present invention combines the advantages of SiO.sub.2 and low dielectric constant materials by creating a multilayer dielectric stack of alternating layers of low-k materials and traditional dielectrics. A stabilizing layer is inserted between layers of low-k films. Since the thickness of problematic low-k materials remain less than the cracking threshold, many of the problems discussed above are alleviated. The stabilizing prevents the nucleation and propagation of micro cracks. In a preferred embodiment, interconnect lines 14 are first patterned and etched on a substrate 10. A low-k material such as hydrogen silsesquioxane (HSQ) 18 is spun across the surface of the wafer to fill areas between interconnect lines. The HSQ is then heated on a hot plate to cure. A thin dielectric stabilizing layer such as SiO.sub.2 20 can then be applied to on top of the low-k material. A thick SiO.sub.2 planarization layer 22 may then be applied and planarized. In other embodiments, the HSQ and SiO.sub.2 process steps can be repeated for multiple layers of HSQ.

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