Method for fabricating a mesa transistor-trench capacitor memory

Details Method for fabricating a mesa transistor-trench capacitor memory Method for fabricating a mesa transistor-trench capacitor memory

1990-06-29

1991-01-29

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 60, 437 89, 437191, 437228, 437203, 437233, 437919, H01L 2170

Patent

active

049886371

ABSTRACT:
A method is described for fabricating a DRAM cell in a monocrystalline substrate wherein the cell includes an FET transistor and a capacitor. The method includes the steps of providing a buried storage capacitor in a trench in the substrate; forming a semiconductor mesa area juxtaposed to the buried storage capacitor; opening a channel to a contact of the storage capacitor; depositing a semiconductor layer over the mesa area and in the opened channel; removing a substantial portion of the conductive layer while leaving at least a connecting portion of the conductive layer deposited in the channel and in communication with the semiconductor mesa; and forming an FET gate structure including a source and drain on the mesa whereby the connecting conductive portion provides a conductive path between the FET and the capacitor.

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