Method of manufacturing non-volatile semiconductor memory device

Details Method of manufacturing non-volatile semiconductor memory device Method of manufacturing non-volatile semiconductor memory device

1989-05-24

1991-01-29

Hearn, Brian

Fishing, trapping, and vermin destroying

437 49, 437 52, 437195, 357 235, H01L 21265

Patent

active

049886355

ABSTRACT:
A memory cell of 1 bit is constituted by 1 selecting transistor and 1 memory transistor in an EEPROM. One of the source-drain regions is commonly used by the selecting transistor and the memory transistor. The commonly used source-drain region is manufactured through the following steps. First, a gate electrode of the transistor is formed. An oxide film is deposited on the entire surface. A resist is applied thereon and is etched back to expose a surface of the oxide film on the gate electrode. Thereafter, the oxide films deposited on the side surfaces of the gate electrode are removed to form opening portions. Impurities are implanted to the silicon substrate utilizing the opening portions.

REFERENCES:
patent: 4417264 (1983-03-01), Angle
patent: 4462090 (1984-07-01), Iizuka
patent: 4513397 (1982-12-01), Ipri et al.
patent: 4775642 (1988-10-01), Chang et al.
J. Yeargain & C. Kuo, "A High Density Floating-Gate Eeprom Cell", IEEE (1981), pp. 24-27.

Affiliated with

Also associated with

Rating

Method of manufacturing non-volatile semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing non-volatile semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing non-volatile semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-813242