Minimum latency bus interface circuit with reduced I/O pin count

Details Minimum latency bus interface circuit with reduced I/O pin count Minimum latency bus interface circuit with reduced I/O pin count

1997-04-30

1997-12-02

Shah, Alpesh M.

Boots, shoes, and leggings

395309, 395550, 3642328, 3642405, 3642715, 364DIG1, G06F 1300

Patent

active

056946147

ABSTRACT:
A method and apparatus for interfacing multiple integrated circuit chip devices to a system bus includes higher speed portions of a circuit within a primary IC chip and lower speed portions of a circuit within a secondary IC chip. The primary IC chip connects directly to the system bus while the secondary IC chip receives the same bus signals via the primary IC chip after a one clock cycle delay. Both the primary and secondary IC chips are capable of driving signals out onto the system bus when the primary and secondary ICs are part of a bus master circuit. When the primary and secondary ICs act as bus masters, signals are received by the secondary IC chip in the same clock cycle as the primary IC chip receives the signals. Thus, the secondary IC includes a state machine to indicate if the received signals are delayed by one clock cycle or not. In a preferred embodiment, the same pins are used by the primary IC to drive signals through to the secondary IC as to drive signals out onto the system bus.

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