Time slot interchange digital switched matrix

Details Time slot interchange digital switched matrix Time slot interchange digital switched matrix

1986-12-08

1988-09-13

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 58, H04J 302

Patent

active

047714204

ABSTRACT:
A time slot interchange matrix is comprised of a plurality of matrix modules (50)-(56) each for receiving data on a plurality of channels and transmitting data on the same number of channels. Each of the modules consists of separate banks of random access memory that are interfaced with an intramatrix bus (70) for receiving data from each of the matrix modules in the system for storage therein during a collection frame. During a transmission frame, this information is randomly accessed in accordance with an interconnect pattern stored in a control RAM (122) for output from the digital matrix module. Each digital matrix module stores all of the information in the system such that the system is non-blocking for any given channel stored and such that information is not impeded by the interconnect pattern of another digital matrix module.

REFERENCES:
patent: 3678205 (1972-07-01), Cohen et al.
patent: 4320501 (1982-03-01), Le Dieu et al.
patent: 4450557 (1984-05-01), Munter
patent: 4455648 (1984-06-01), Binz et al.
patent: 4470139 (1984-09-01), Munter

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