Multi-processor reconfigurable in single instruction multiple da

Details Multi-processor reconfigurable in single instruction multiple da Multi-processor reconfigurable in single instruction multiple da

1989-11-17

1993-05-18

Lee, Thomas C.

Boots, shoes, and leggings

395425, 364DIG1, 3642319, 3642431, 3642281, 3642287, 3642288, G06F 900, G06F 1516

Patent

active

052127770

ABSTRACT:
There is disclosed a multiprocessor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories are contained on a single silicon chip. Each processor can operate to execute the same instruction at the same time (SIMD mode) or different instructions at the same time (MIMD mode).

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