Controllably operable method and apparatus for predicting addres

Details Controllably operable method and apparatus for predicting addres Controllably operable method and apparatus for predicting addres

1992-02-26

1997-12-02

Geckil, Mehmet B.

395403, 395800, G06F 1300

Patent

active

056945728

ABSTRACT:
In a data processing system which employs a cache memory feature, a method and exemplary special purpose apparatus for practicing the method are disclosed to lower the cache miss ratio for called operands. Recent cache misses are stored in a first in, first out miss stack, and the stored addresses are searched for displacement patterns thereamong. Any detected pattern is then employed to predict a succeeding cache miss by prefetching from main memory the signal identified by the predictive address. The apparatus for performing this task is preferably hard wired for speed purposes and includes subtraction circuits for evaluating variously displaced addresses in the miss stack and comparator circuits for determining if the outputs from at least two subtraction circuits are the same indicating a pattern yielding information which can be combined with an address in the stack to develop a predictive address. The cache miss prediction mechanism is only selectively enabled during cache "in-rush" following a process change to increase the recovery rate; thereafter, it is disabled, based upon timing-out a timer or reaching a hit ratio threshold, in order that normal procedures allow the hit ratio to stabilize at a higher percentage than if the cache miss prediction mechanism were operated continuously.

REFERENCES:
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patent: 5269013 (1993-12-01), Abramson et al.
patent: 5305389 (1994-04-01), Palmer
patent: 5367656 (1994-11-01), Ryan
IBM Technical Disclosure Bulletin, "New Context Bit", IBM Technical Disclosure Bulletin, vol. 30, No. 2, Jul. 1987.

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