Internal address determining device for semiconductor memory dev

Details Internal address determining device for semiconductor memory dev Internal address determining device for semiconductor memory dev

1991-03-13

1993-05-18

Zazworsky, John

Static information storage and retrieval

Addressing

Multiplexing

36518902, 36518903, G11C 800, G11C 804

Patent

active

052126650

ABSTRACT:
An internal address determining device for a semiconductor memory device has a refresh counter storing refresh addresses and an expanded nibble counter storing nibble addresses. External row and column addresses and a strobe signal are input to an input section. The device also has first and second multiplexers, first and second latch circuits for latching output from the first and second multiplexers, respectively, and a timing circuit for controlling operation timing of the first and second multiplexers by generating one of an external row address signal select signal, an external column address select signal, a refresh address select signal, and a nibble address select signal. In response to one of those control signals, one of the multiplexers selects and outputs a corresponding address signal.

REFERENCES:
patent: 4939695 (1990-07-01), Isobe et al.
patent: 5146430 (1992-09-01), Torimaru et al.
patent: 5155705 (1992-10-01), Goto et al.
Excerpt of a lecture entitled "Study of Address Buffers for Common-Address-Bus" made in 70th Anniversary National Conference held at The Institute of Electronics, Information and Communication Engineers, 1987.

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