Scan path generation with flip-flop rearrangement according to g

Details Scan path generation with flip-flop rearrangement according to g Scan path generation with flip-flop rearrangement according to g

1990-03-12

1993-05-18

Dixon, Joseph L.

Boots, shoes, and leggings

371 221, 364489, G06F 1560

Patent

active

052126510

ABSTRACT:
In a scan path generation system, flip-flops and logic elements of a logic circuit are placed on an X-Y plane according to logical connection data and original scan path data. Data describing a sequence in which the flip-flops are to be arranged for the benefit of the geometry of the logic circuit is prepared and stored in a sequence table. The flip-flops on the X-Y plane are rearranged according to the data stored in the sequence table. New scan path data is derived from the rearranged flip-flops and are substituted for the original scan path data to be used for connecting the flip-flops. Due to the rearrangement process, the flip-flops can be connected in a scan path with relatively short and straight path sections between successive flip-flops, minimizing the amount of channel space which is occupied by the scan path.

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Trischler, E. "Incomplete Scan Path with an Automatic Test Generation Methodology", IEEE Digest of Papers, 1980 Test Conference (pp. 153-163) reprinted as pp. 263-272, 1980.

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