Fabrication method for high power MOS device

Details Fabrication method for high power MOS device Fabrication method for high power MOS device

1981-09-09

1983-08-16

Andrews, M. J.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 29580, 29591, 156648, 357 23, 357 55, 357 59, H01L 21467

Patent

active

043983391

ABSTRACT:
This disclosure relates to a high power VMOS semiconductor device and fabrication method therefor. This VMOS semiconductor device uses a doped polysilicon gate electrode in the V groove and an overlying metal electrode located over an insulation layer protecting the doped polysilicon gate electrode. This overlying metal electrode layer covers substantially the entire surface area (except for a small area where electrical contact is made to the doped polysilicon gate electrode) of one surface of the device. Another embodiment discloses the use of a self-aligned metal contact to the source or drain region of the VMOS device between adjacent V groov

REFERENCES:
patent: 3993515 (1976-11-01), Reichert
patent: 4048649 (1977-09-01), Bohn
patent: 4065783 (1977-12-01), Ouyang
patent: 4070690 (1978-01-01), Wickstrom
patent: 4105475 (1978-08-01), Jenne
patent: 4222063 (1980-09-01), Rodgers
Rodgers et al., "VMOS Memory Technology" 1977 IEEE International Solid-State Circuits Conf., Digest of Techn. Papers, pp. 74, 75, 239.

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