Encoder and decoder of an error correcting code

Details Encoder and decoder of an error correcting code Encoder and decoder of an error correcting code

1996-03-21

1997-12-02

Baker, Stephen M.

Excavating

371 376, H03M 1300

Patent

active

056944055

ABSTRACT:
An encoder and a decoder of an error correction code. A first division pattern generating circuit generates an n bit first division pattern used for dividing inputted n significant bit data in the next cycle from an n bit remainder obtained by dividing inputted data until then and inputted n less significant bit data. A second division pattern generating circuit generates an n bit second division pattern for dividing inputted n less significant bit data from the n bit remainder obtained by dividing inputted data until then. Therefore, the present invention provides the encoder and the decoder of a 2n parallel error correcting code which allows data to be coded and decoded, irregardless of whether the error correcting code is in the n more significant bits or the n less significant bits of a 2n parallel data bus.

REFERENCES:
patent: 5230002 (1993-07-01), Yamashita et al.
patent: 5282215 (1994-01-01), Hyodo et al.
patent: 5345451 (1994-09-01), Uriu et al.
patent: 5383203 (1995-01-01), Miyazono
patent: 5402429 (1995-03-01), Stessens
patent: 5570377 (1996-10-01), Merino Gonzalez et al.
de Prycker, "Asynchronous Transfer Mode Solution for Broadband ISDN", Chapter 3, Section 3.5, pp. 122-125, (1993).
ITU-T Recommendation I.432, "B-ISDN User-Network Interface-Physical Layer Specification", Chapter 4, pp. 157,179-180, (1993).

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