Semiconductor memory device having layout area of periphery of o

Details Semiconductor memory device having layout area of periphery of o Semiconductor memory device having layout area of periphery of o

1996-07-08

1997-12-02

Nelms, David C.

Static information storage and retrieval

Format or disposition of elements

365 63, G11C 506

Patent

active

056943520

ABSTRACT:
A semiconductor memory device includes four memory cell arrays, four output pads formed in a linear manner at the center of a semiconductor substrate, four output control circuits for generating readout data signals and control signals, four signal generation circuits responsive to the readout data signals for generating complementary pairs of data signals, and responsive to the control signals, four signal line groups including four signal lines connected between the output control circuits and the signal generation circuits, four output drivers responsive to pairs of data signals for supplying data to the output pads, and four signal line pairs connected between the signal generation circuits and output drivers. Signal generation circuits of great size are arranged at the center of the semiconductor substrate where the layout margin is great, and only the output driver is arranged in the proximity of the output pad where the layout margin is small. Therefore, the chip area is reduced. Access is speeded since the signal lines forming the signal line group are shorter in length, though greater in number, than the signal lines forming the signal line pair.

REFERENCES:
patent: 5436865 (1995-07-01), Kitazawa
patent: 5500817 (1996-03-01), McLaury
patent: 5532961 (1996-07-01), Mori

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