Process for global planarizing of surfaces for integrated semico

Details Process for global planarizing of surfaces for integrated semico Process for global planarizing of surfaces for integrated semico

1990-09-10

1993-05-18

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437193, 437195, 437228, 437231, H01L 2188, H01L 21302

Patent

active

052121143

ABSTRACT:
In a process for global planarizing of surfaces for integrated semiconductor circuits a locally planarized insulation layer of silicon oxide with one thickness is initially applied on a structured layer to be planarized having another thickness. Photoresist structures are generated thereon as an auxiliary plane inversely to the structured plane lying below. A further well-adhering and planarizing auxiliary layer, preferably formed of spin-on glass, is applied. It must be selected as a function of a following anisotropic back-etching, in such a way that its etching rate is greater than that of the photoresist layer and nearly the same as that of the silicon oxide layer. The photoresist structures remaining after the back etching are removed. A further insulating layer formed of silicon oxide is applied up to the selected insulator thickness. The process is characterized by uncritical, well controllable process steps in contemporary technology and is usable in highly integrated circuits with a plurality of metallizing planes as well as in simple component structures.

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Spindler, et al., "Trends and New Applications in Thin Films" (TATF 89/Reg. No. 48) Siemens AG Munich, Feb./Mar. 1989.

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