Fishing – trapping – and vermin destroying
Patent
1992-05-26
1993-05-18
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 72, 437 89, 437 90, 148DIG50, H01L 2176
Patent
active
052121100
ABSTRACT:
A process for fabricating isolation regions in a semiconductor substrate which does not depend upon pattern definition capability. In one embodiment a device isolation region (30) is formed in a semiconductor substrate (12) by first creating a trench (18) in the substrate (12). A single-crystal SiGe layer (24) is formed to overlie the wall surface (20) of the trench (18). A layer of selectively-deposited, single-crystal silicon (26) is formed in the trench (18) using both the bottom surface (22) of the trench (18) and the SiGe layer (24) as a nucleation site for the selective deposition process. After the single-crystal silicon layer (26) is formed, the SiGe layer (24) is selectively removed and the previously occupied space is filled with a dielectric material to form isolation region (30).
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patent: 4666556 (1987-05-01), Fulton et al.
patent: 4849371 (1989-07-01), Hansen et al.
patent: 4942137 (1990-07-01), Sivan et al.
N. Kasai, et al. "1/4 .mu.m CMOS Isolation Technique With Sidewall Insulator and Selective Epitaxy", IEEE Int. Electron Device Meet., Washington, D.C., Dec. 1985, pp. 419-422.
Kirsch Howard C.
Pfiester James R.
Dang Trung
Dockrey Jasper W.
Hearn Brian E.
Motorola Inc.
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