Method for forming PN junction isolation regions by forming buri

Details Method for forming PN junction isolation regions by forming buri Method for forming PN junction isolation regions by forming buri

1991-09-20

1993-05-18

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 79, 437 78, 437 66, 437 62, 437 74, H01L 2176

Patent

active

052121097

ABSTRACT:
In a semiconductor device having island regions formed in a surface area of a substrate, the island regions are electrically isolated from the substrate via buried regions formed of polycrystalline or amorphous semiconductor, without use of epitaxial growth technique. Since the polycrystalline or amorphous semiconductor includes a great number of recombination centers, parasitic operation between the elements formed on the semiconductor substrate can be prevented. Further, the buries regions are excellent in heat conductivity, the breakdown resistance against surge voltages or static electricity can be improved. Furthermore, when applied to a CMOS, it is possible to prevent latch up action caused by a parasitic thyristor formed in the CMOS, by the presence of the buried regions including a great number of recombination centers.

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