Method for manufacturing an MOS transistor

Details Method for manufacturing an MOS transistor Method for manufacturing an MOS transistor

1992-03-09

1993-05-18

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 44, 437 45, 437164, 437 89, 437108, H01L 21265

Patent

active

052121046

ABSTRACT:
A method for the manufacture of an MOS transistor. A channel region is produced by selective epitaxy on a substrate (1) doped with a first conductivity type, said channel region containing a delta-shaped layer (5) doped with the first conductivity type. Source region (13) and drain region (14) are formed, in particular, by drive-out from a doped glass layer (12).

REFERENCES:
patent: 4902643 (1990-02-01), Shimawaki
patent: 5008211 (1991-04-01), Yamazaki
Van Gorkum et al., "Atomic Layers Doping (ALD) Technology in Si and its Application to a New Structure FET", Journal of Crystal Growth, vol. 95, No. 1-4, Feb. 1989, pp. 480-483.
Yamaguchi et al., "A New Short Channel MOSFET with an Atomic Layer Doped Impurity Profile (ALD MOSFET)", Japanese Journal of Applied Physics, vol. 22, No. 22, 1983, pp. 267-270 Supplement 22-1.
"Hot-Carrier Injection Suppression Due to the Nitride-Oxide LLD Spacer Structure", by T. Mizuno, IEEE Transactions of Electron Devices, vol. 38, No. 3, Mar. 1991, pp. 584-589.
".pi.-Heterostructure Field Effect Transistors for VLSI Applications" by K. Lee et al, IEEE Transactions on Electron Devices, vol. 37, No. 8, Aug. 1990, pp. 1810-1820.

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