Versatile CMOS decoder

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307205, 307DIG5, 340347DD, H03K 1760, H03K 518, H03K 1300

Patent

active

041762878

ABSTRACT:
A CMOS decoder capable of providing a one of n, a two of n, or a three of n decoded output, where n is equal to the number of outputs of the decoder and is a function of the number of bits in a digital signal to be decoded. A first plurality of transistors are used to precharge each of the decoder's outputs to a first voltage potential. A second plurality of transistors are placed in series between the first node and each of the outputs. The second plurality of transistors are controlled by the coded digital signal that is being decoded. The number of decoded outputs can be varied by connecting some of the outputs to some of the transistors of the second plurality of transistors or by connecting others of the outputs to junctions formed by the series placed transistors. In a preferred embodiment, a pair of back-to-back inverters are connected to each of the outputs to provide a static decoder.

REFERENCES:
patent: 3766408 (1973-10-01), Suzuki et al.
patent: 3784978 (1974-01-01), Zola
patent: 3873851 (1975-03-01), Weimer
patent: 3896429 (1975-07-01), Moyer et al.
patent: 3984703 (1976-10-01), Jorgensen
patent: 3989955 (1976-11-01), Suzuki
patent: 4021656 (1977-05-01), Caudel et al.
patent: 4103349 (1978-07-01), Marmet
patent: 4104735 (1978-08-01), Hofmann et al.
Electronics (pub.); "COS/MOS: The Best of Both Worlds", pp. 109-112, 2/17/1969; author Herzog.
Kenyon et al., "Complementary Field-Effect Transistor High-Density Decoder", IBM Tech. Discl. Bull., pp. 2823-2824; vol. 15, No. 9, 2/1973.

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