Semiconductor integrated circuit capable of preventing occurrenc

Details Semiconductor integrated circuit capable of preventing occurrenc Semiconductor integrated circuit capable of preventing occurrenc

1992-06-08

1994-07-05

Clawson, Jr., Joseph E.

Static information storage and retrieval

Addressing

Sync/clocking

365194, 365206, 36523003, 365214, 307481, 307594, G11C 800

Patent

active

053273923

ABSTRACT:
A semiconductor integrated circuit includes a circuit block whose operation is controlled by a inverted control signal whose significant potential level is set at a ground potential, and a wiring for transmitting a control signal for controlling the operation of the circuit block. An inverting circuit provided near the circuit block inverts the control signal and then supplies the inverted signal to the circuit block via a wiring. The inverter includes a first capacitor connected between the power source terminal and a node which is set at a high potential level in the inverter circuit when the control signal is set at the non-significant potential level and a second capacitor connected between a ground potential terminal and a node which is set at a ground potential level when the control signal is set at the non-significant potential level.

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Motorola Memory Data Manual, Series B, .COPYRGT.1980 Motorola, Inc., pp. 3-27 to 3-30.
National Semiconduictor "Memory Databook," .COPYRGT.1977, MM54C89/MM74C89, pp. 3-1 to 3-4.

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