Error correction and detection systems

Details Error correction and detection systems Error correction and detection systems

1977-12-22

1979-11-27

Atkinson, Charles E.

Registers

Systems controlled by data bearing records

Time analysis

G06F 1112, G11C 2900

Patent

active

041756924

ABSTRACT:
An error correction and detection system is capable of detecting a miscorrection caused by a triple bit error by using SEC-DED code and is adapted to correct a single bit error and detect a double bit error. When the single bit error is detected from the SEC-DED code read out from a memory, the code is subjected to a retrial process after correction of the error, wherein the corrected SEC-DED code is rewritten in the memory after inversion of the polarity thereof and is read out therefrom. The code read out from the memory undergoes again an error checking process after inversion of the polarity thereof. Repeated detection of an error indicates that the first correction was a miscorrection as caused by the triple bit error.

REFERENCES:
patent: 3648238 (1972-03-01), Yarrington
patent: 3688265 (1972-08-01), Carter et al.
patent: 3825893 (1974-07-01), Bossen et al.
patent: 3949208 (1976-04-01), Carter
patent: 4030067 (1977-06-01), Howell et al.
patent: 4037091 (1977-07-01), Beuscher
patent: 4045779 (1977-08-01), Markle

Affiliated with

Also associated with

Rating

Error correction and detection systems does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Error correction and detection systems, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Error correction and detection systems will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-799061