Intergrated circuit having testing function circuit and control

Details Intergrated circuit having testing function circuit and control Intergrated circuit having testing function circuit and control

1988-11-15

1990-03-20

Smith, Jerry

Excavating

371 151, G01R 3128

Patent

active

049107348

ABSTRACT:
A plurality of testing circuits formed of parallel registers are incorporated between a plurality of circuit portions constituting a data processing circuit. Each parallel register comprises scan latch circuits whose number corresponding to the number of sets of input and output terminals of the circuit portion. A first input terminal of each scan latch circuit is connected to an output terminal of the corresponding circuit portion, a second input terminal is connected to an input terminal of the corresponding circuit portion, an output terminal is connected to an input terminal of another circuit portion, respectively, control terminals of the scan latch circuits are connected together in each register to which a control signal is inputted. The testing circuit serves to test the circuit portion or operate the circuit portion upon reception the control signal corresponding to the test mode or the operation mode. The control signal is outputted by a control circuit having two input terminals, and it changes dependent on the combination of signals inputted to the input terminals.

REFERENCES:
patent: 4317200 (1979-10-01), Wakatsuki et al.
patent: 4503386 (1982-04-01), Das Gupta et al.
patent: 4513418 (1985-04-01), Bardell
patent: 4519078 (1982-09-01), Komonytsky
patent: 4553236 (1985-11-01), Zasio
patent: 4597042 (1986-06-01), d'Angeal
patent: 4680733 (1984-10-01), Duforestel et al.
patent: 4697267 (1987-09-01), Wakai
patent: 4698588 (1985-10-01), Hwang et al.
patent: 4701921 (1987-10-01), Powell
patent: 4701922 (1987-10-01), Kuboki
patent: 4710931 (1987-12-01), Bellay
patent: 4710933 (1987-12-01), Powell
patent: 4728883 (1985-03-01), Green
patent: 4764926 (1985-12-01), Knight et al.
patent: 4780666 (1987-08-01), Sakashita
C. Mead and L. Conway, "Introduction to VLSI Systems", (1980); 66, 67.
C. Mead and L. Conway, "Introduction to VLSI Systems", (1980): 102, 109.
F. Tsui, "LSI/VSLI Testability Design", Chapter 5, Latch Scanning Arrangements (LSA), (1986): 102, 109.

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