Dynamic shift register utilizing CMOS dual gate transistors

Details Dynamic shift register utilizing CMOS dual gate transistors Dynamic shift register utilizing CMOS dual gate transistors

1982-05-03

1984-09-18

Miller, Stanley D.

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

Particular transfer means

307443, 307451, 357 23MG, 357 86, 357 2314, 377 80, G11C 1928, H03K 1704, H03K 17687, H03K 19017

Patent

active

044728212

ABSTRACT:
A shift register using dual gate transistors is described. Each stage consists of a P-channel and and N-channel dual gate transistor interconnected to provide both an inverting function and a switching function. The gates of each stage of one set of alternate stages are clocked in one phase with a clocking voltage alternating between a low level and a high level and its inverse. The gates of each stage of the other set of alternative stages are clocked in the opposite phase with the clocking voltage and its inverse.

REFERENCES:
patent: 3715637 (1973-02-01), Poirier
patent: 4101790 (1978-07-01), Ebihara et al.
patent: 4306352 (1981-12-01), Schrader
patent: 4319263 (1982-03-01), Rao
patent: 4395774 (1983-07-01), Rapp
W. P. Noble, Jr.; "Short-Channel Effects in Dual-Gate Field-Effect Transistors," in IEEE Int. Electron Dev. Mtg., Dig. Tech. Papers, Dec. 1978, pp. 483-486.
Hans G. Dill, "A New Insulated Gate Tetrode With High Drain Breakdown Potential and Low Miller Feedback Capacitance," IEEE Transactions on Electron Devices, Vol. ED-15, No. 10, Oct. 1968.

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