Shift circuit having a plurality of cascade-connected data selec

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364715, G06F 700

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active

044727887

ABSTRACT:
A shift circuit comprises a plurality of stages of data selectors, a first data selector, a second data selector and a temporary register. The data selectors shift an n-bit input data by m bits which are specified by a shifting amount data and produces a first output data or a second output data. The first and second data selectors selectively output the first and second output data in accordance with shift direction. The temporary register comprises n bits for storing a data which is not selected by said first or second data selector.

REFERENCES:
patent: 3810115 (1974-05-01), Stafford
patent: 3961750 (1976-06-01), Dao
patent: 4122534 (1978-10-01), Casaratto
patent: 4345316 (1982-08-01), Hirotani et al.
Weinberger, "Arithmetic Shift" IBM Tech. Disclosure Bulletin vol. 19, No. 1, Jun. 1976 pp. 207-216.
Gersbach "High-Speed Shifter Array" IBM Tech. Disclosure Bulletin vol. 21, No. 4, Sep. 1978 pp. 1379-1380.
Houghtalen "Microprocessor with External Shift Capability" IBM Tech. Disc. Bulletin vol. 22, No. 7 Dec. 1979 p. 2714.
Gersbach "Algebraic/Logical Shift Matrix" IBM Tech. Disc. Bulletin vol. 23, No. 1, Jun. 1980 pp. 120-122.

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