Instruction decoding logic system

Details Instruction decoding logic system Instruction decoding logic system

1981-09-16

1984-09-18

Atkinson, Charles E.

Boots, shoes, and leggings

G06F 100

Patent

active

044727739

ABSTRACT:
A decoding logic system in a logic control system of a data processing system is disclosed, wherein the data processing system is comprized of a main memory unit communicating with the logic control system by way of a common communication bus, and wherein the logic control system and a CPU (central processing unit) communicate by way of a local communication bus. In response to a CPU request, CPU instructions stored in the main memory unit are received by the logic decoding system, and presented to the CPU in such a manner as to accommodate both memory bit and CPU computed bit modifications to the instructions during instruction execution, while avoiding interruptions in CPU activity caused by information transfer delays internal to the logic decoding system. Instruction modification also may be effected by incrementing or decrementing the instructions under firmware control.

REFERENCES:
patent: 4109311 (1978-08-01), Blum et al.
patent: 4115850 (1978-09-01), Houston et al.
patent: 4247893 (1981-01-01), Anderson et al.
patent: 4309753 (1982-01-01), Negi et al.

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