Synthesizer for generating a logic network using a hardware inde

Details Synthesizer for generating a logic network using a hardware inde Synthesizer for generating a logic network using a hardware inde

1995-06-07

1996-12-03

Coleman, Eric

Boots, shoes, and leggings

3642756, 3642751, 3642274, 364DIG1, G06F 1560

Patent

active

055817815

ABSTRACT:
A method and system are provided for generating a logic network using a hardware independent description means. A logic circuit synthesizer, in response to a user description specifying only signals and the circumstances under which the signals are produced, generates a logic network that generates the signals specified in the user description, e.g., a net list of logic elements, such as logic gates, high impedance drivers, level sensitive latches and edge sensitive flip-flops along with the interconnections of the logic elements. In one embodiment, the logic circuit synthesizer includes a preprocessor means and a logic circuit generator means. The preprocessor means, in response to the user description, converts signals and conditions in the user description into a structure having nodes interconnected by edges. The edges include an edge condition under which the edge is traversed. The logic circuit generator, using the structure and the edge conditions, creates a logic network that generates the signals specified in the user description.

REFERENCES:
patent: 4882690 (1989-11-01), Shinsa
patent: 4896272 (1990-01-01), Kurosawa
patent: 5029102 (1991-07-01), Drumm
VHDL-The Language by Roger Lipsett et al., IEEE Design & Test, Apr. 1986 pp. 28-41.
VHDL-The Designer Environment by Alfred S-Gilman, IEEE Design & Test, Apr. 1986, pp. 42-47.

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