Centralized control SIMD processor having different priority lev

Details Centralized control SIMD processor having different priority lev Centralized control SIMD processor having different priority lev

1994-07-20

1996-05-28

An, Meng-Ai

Boots, shoes, and leggings

395729, 395732, 395860, 395299, 36492795, 3649314, 3642404, 3642419, 364DIG1, G06F 1318, G06F 1516

Patent

active

055220800

ABSTRACT:
Features which support conditional execution and sequencing are employed in concert with a centralized-control, single-instruction, multiple data integrated video signal processor, thus adapting efficiently to the high degree of parallelism inherent in this type of video signal processing systems. A three-level prioritization scheme is used to handle the input/output data stream to improve the throughput of the processor, including provisions for distinguishing between same-priority events occurring at different times, and ensuring that in such cases the requested operations occur in the same temporal order as the respective requests.

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P. W. Dandekar et al; "Effect of Different Arbitration Priority Stategies on Throughput of a Memory-Coupled Multiprocessor with HBO"; IEEE 1990 pp. 485-487.

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