Method and apparatus for back-annotating timing constraints into

Details Method and apparatus for back-annotating timing constraints into Method and apparatus for back-annotating timing constraints into

1993-06-07

1996-12-03

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364490, 364578, 326 38, G06F 1700

Patent

active

055817386

ABSTRACT:
A method and apparatus for back-annotating timing constraints onto a logical simulation model of a field programmable gate array circuit includes a process and system for creating equations relating to the sequence of nodes between an input and output or clock input in the logical circuit and equating this to the external timing characteristics of the FPGA circuit. This linear system of equations can then be solved to obtain the individual timing constraints for each node of the circuit within the simulation model.

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Cherry, "Pearl: A CMOS Timing Analyzer", IEEE, 1988 Mar., pp. 148-153.
Press, William H. et al. Numerical Recipes in C "Solution of Linear Algebracia Equations", 1988, pp. 28-46 (Month is not available).

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