Programmable logic device having low power microcells with selec

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

3074651, H03K 19173

Patent

active

052988031

ABSTRACT:
A programmable logic device (PLD) is disclosed which has an output macrocell. The macrocell selectively produces either a registered and inverted registered set of signals, or a combinatorial or inverted combinatorial set of signals, but not both set of signals.

REFERENCES:
patent: 3287702 (1966-11-01), Borck, Jr. et al.
patent: 3287703 (1966-11-01), Slotnick
patent: 3296426 (1967-01-01), Ball
patent: 3313926 (1967-04-01), Minnick
patent: 3423646 (1969-01-01), Cubert et al.
patent: 3462742 (1969-08-01), Miller et al.
patent: 3473160 (1969-10-01), Wahestrom
patent: 3514543 (1970-11-01), Crawford et al.
patent: 3535498 (1970-10-01), Smith, Jr.
patent: 3566153 (1971-02-01), Spencer, Jr.
patent: 3602733 (1971-08-01), Aoki
patent: 3702985 (1972-11-01), Probsting
patent: 3737866 (1973-06-01), Gruner
patent: 3757306 (1973-09-01), Boone
patent: 3769525 (1973-10-01), Foss et al.
patent: 3774171 (1973-11-01), Regetz
patent: 3792242 (1974-02-01), Preel
patent: 3795901 (1974-03-01), Boehm et al.
patent: 3798606 (1974-03-01), Henle et al.
patent: 3803587 (1974-04-01), Mead
patent: 3816725 (1974-06-01), Greer
patent: 3818252 (1974-06-01), Chiba et al.
patent: 3818452 (1974-06-01), Greer
patent: 3832489 (1974-08-01), Kreshna
patent: 3849638 (1974-11-01), Greer
patent: 3906255 (1975-09-01), Mensch, Jr.
patent: 3912947 (1975-10-01), Buchanan
patent: 3924243 (1975-12-01), Vermeulen
patent: 3967059 (1976-06-01), Moore, III et al.
patent: 3974366 (1976-08-01), Hebenstreit
patent: 3979730 (1976-09-01), Bennett et al.
patent: 3983538 (1976-09-01), Jones
patent: 3987410 (1976-10-01), Beausoleil et al.
patent: 3990045 (1976-11-01), Beausoliel et al.
patent: 4034349 (1977-07-01), Monaco et al.
patent: 4034356 (1977-07-01), Howley et al.
patent: 4037089 (1977-07-01), Horninger
patent: 4044312 (1977-08-01), D'Ortenjio
patent: 4078259 (1978-03-01), Soulsby et al.
patent: 4091359 (1978-05-01), Rossier
patent: 4093998 (1978-06-01), Miller
patent: 4107785 (1978-08-01), Seipp
patent: 4124899 (1978-11-01), Birkner et al.
patent: 4128873 (1978-12-01), Lamlaux
patent: 4218740 (1980-08-01), Bennett et al.
patent: 4422072 (1983-12-01), Cavlan
patent: 4554640 (1985-11-01), Wong et al.
patent: 4717912 (1988-01-01), Harvey et al.
patent: 4742252 (1988-05-01), Agrawal
patent: 4758746 (1988-07-01), Birkner
patent: 4763020 (1988-08-01), Takata et al.
patent: 4771285 (1988-09-01), Agrawal et al.
patent: 4789951 (1988-12-01), Birkner
patent: 4847612 (1988-07-01), Kaplinsky
patent: 4879481 (1989-11-01), Pathak
patent: 4918641 (1990-04-01), Jigour et al.
patent: 4963768 (1990-10-01), Agrawal et al.
patent: 4967107 (1990-10-01), Kaplinsky
patent: 5012135 (1991-04-01), Kaplinsky
patent: 5027011 (1991-06-01), Steele
patent: 5027315 (1991-06-01), Agrawal et al.
patent: 5028821 (1991-07-01), Kaplinsky
patent: 5055718 (1991-10-01), Galbraith et al.
patent: 5059828 (1991-10-01), Tanagawa
patent: 5121006 (1992-06-01), Redusen
patent: 5136188 (1992-08-01), Ha et al.
patent: 5148391 (1992-09-01), Zagar
patent: 5166556 (1992-11-01), Hsu et al.
patent: 5168177 (1992-12-01), Shankar et al.
H. Fleisher et al "An Introduction To Array Logic" IBM J. Res. Development, p. 132.
"User-Programmable Logic Devices Add Erasability and Hit New Density Levels", Electronic Products, p. 276.
Use of Laser Mechanicm in Priorities Breaks Price and Maintenance Barriers, Jan. 15, 1985 p. 277.
J. E. Elliott, et al., "Array Logic Processing", IBM, Tech. Disclosure Bulletin, vol. 18 No. 21, Jul. 1973, pp. 219 & 220.
H. Fleisher, et al., "Reconfigurable Machine", IBM Tech. Disclosure Bulletin, vol. 16 No. 10 Mar. 1974, pp. 221, 222 & 223.
H. Fleisher et al, "An Introduction to Array Logic" IBM J. Research & Development, Mar. 1975 pp. 98-104.
Jones "Array Logic Macros" IBM J. Research and Development Mar. 1975, pp. 120-126.
Andres, "MOS Programmable Logic Arrays" A Texas Instrument Application Report Oct. 1970 pp. 1-13.
Barna et al, Integrated Circuits in Digital Electronics John Wiley & Sons 1973, pp. 412-419 and 84-91 and FIGS. 11-34.
Wood "High-Speed Dynamic, Programmable Logic Array Chip" IBM J. Res. Develop. Jul. 1975, pp. 379-381.
Boysel, "Memory on a Chip: a step toward large-scale integration" Electronics, Feb. 6, 1967 pp. 93-97.
Wilkes et al "The design of the Control Unit of an Electronic Digital Computer" The Institution of Electrical Engineers, Jun. 1957, pp. 121-128.
Mrazek, "PLAS Replace ROMs per Logic Designs" Electronic Design Oct. 25, 1973 pp. 66-70.
Howley et al. "Programmable Logic Array Decoding Technique" IBM Tech. Disclosure Bulletin, vol. 17 No. 10 Mar. 1975-p. 2988.
Henel "The PLA: a different kind of ROM" Electronic Design, Jan. 5, 1976 pp. 78-84.
Kidder, The Soul Of A New Machine, 1982 pp. 118-128 and 268-269.
National Semiconductor Inc. "Data Update MOS." Aug. 1972, pp. 86 and 87.
Blakeslee, Digital Design With Standard MSI and LSI, John Wiley and Sons, 1975, pp. 67-77, 94-99, and 104-105.
PAL Handbook, Monolithic Memories, Inc. 1978 p. N/A.
Hutton et al. "A Simplified Summation Array for Cellular Logic Modules" IEEE Trans. On Computers, Feb. 1974 pp. 203-206.
Programmable Logic-A Basic Guide for the Designer, Data I/O Corp. 1983-pp. 20-25.
The TTL Data Book For Design Engineers, Texas Instruments Inc., 1973 pp. 295, 303, 473, 458 and 480.
Monolithic Memories Inc. Form 10-K, Oct. 3, 1982 Annual Report Pursuant to Section 13 or 15(2) of the Securities Exchange Act of 1934.
"The Role of Software in the Growth of PLDs" The Technology Research Group Letter vol. 1 No. 13, Nov. 1985 p. 3.
Teil et al. "A Logic Minomyer for KLSI PLA Design" ACM IEEE Ninteenth Design Automation Conf. Proceedings Jun. 1982, pp. 156-162.
Harrin "Programmable Logic Devices Gain Software Support" EDN Feb. 9, 1984, pp. 67-74.
Monolthic Memories Annual Report 1981, Letter to Shareholders p. 2.
"Semicustom IC Update, Field Programmable Logic Devices" VISI from the Valley, Hambrecht & Guest Inc. vol. 3 No. 1, Mar. 1986 pp. 4-7.
Phelps, Institutional Research Report on Monolithic Memories, Inc., A publication of Woodman, Kirkpatrick & Gilbrath Aug. 30, 1984.
Wood "High-Speed Dynamic Programmable Logic Array Chip" IBM J. Res. Develop. Jul. 1975, pp. 379-381.
Covlan et al. "Field PLAS Simplify Logic Designs" reprinted from Electronic Design, Sep. 1, 1975.
Signetics BIPOLAR and MOS Memory, Data Manual Signetics Inc, pp. 156-165 Jan. 1979.
Dorman "PLAS on MPs at times they complete at home they cooperate" Electronic Design, 18 Sep. 1, 1976, pp. 24-30.
Elliot et al "Array Logic Processing" IBM Tech. Disclosure Bulletin, vol. 16, No. 2 Jul. 1973 pp. 586-587.
MacWorld, The Macintosh Magazine, May-Jun. 1984.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Programmable logic device having low power microcells with selec does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable logic device having low power microcells with selec, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable logic device having low power microcells with selec will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-794509

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.