Nonvolatile programmable neural network synaptic array

Details Nonvolatile programmable neural network synaptic array Nonvolatile programmable neural network synaptic array

1992-07-08

1994-03-29

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

395 24, 395 25, 257323, H03K 1908

Patent

active

052987965

ABSTRACT:
A floating-gate MOS transistor is implemented for use as a nonvolatile analog storage element of a synaptic cell used to implement an array of processing synaptic cells based on a four-quadrant analog multiplier requiring both X and Y differential inputs, where one Y input is UV programmable. These nonvolatile synaptic cells are disclosed fully connected in a 32.times.32 synaptic cell array using standard VLSI CMOS technology.

REFERENCES:
patent: 4336465 (1982-06-01), Nakano et al.
patent: 4904881 (1990-02-01), Castro
patent: 4942450 (1990-07-01), Iwashita
patent: 4950917 (1990-08-01), Holler et al.
patent: 4978873 (1990-12-01), Shoemaker
patent: 5021693 (1991-06-01), Shima
patent: 5028810 (1991-07-01), Castro et al.
patent: 5055897 (1991-10-01), Canepa et al.
Rosetto et al. "Analog VLSI Synaptic Matrices", IEEE Micro, Dec. 1989, pp. 56-63.
K. Bult and H. Wallinga, "A CMOS Four-Quadrant Analog Multiplier," IEEE Journal of Solid State Circuits, vol. SC-21, No. 3, pp. 430-435, 1986.
J. Alspector and R. Allen, "A Neuromorphic VLSI Learning System," Proc. of the 1987 Stanford Conference, Advanced Research in VLSI, pp. 313-349.
S. Eberhardt, T. Duong, and A. Thakoor, "A VLSI Analog Synapse `Building-Block` Chip for Hardware Neural Network Implementations," Proceedings of the Third Annual parallel Processing Symposium, Fullerton, Ca., Mar. 29-31, 1989.
M. Holler, S. Tam, H. Castro and R. Benson, "An Electrically Trainable Artificial Neural Network (ETANN) with 10240 `Floating Gate` Synapses," (Preprint).
D. Kerns, J. Tanner, M. Sivilotti and J. Luo, "CMOS UV-Writable Non-Volatile Analog Storage," (To appear in the Proceedings of Advanced Research in VLSI: International Conference 1991, Santa Cruz, Ca.
C. Mead and L. Conway, Introduction to VLSI Systems, Addison-Welsey Publishing Co. (1980), pp. 38-45.
J. Babanezhad and C. Gabor, "A 20-V Four Quadrant CMOS Analog Multiplier," IEEE Journal of Solid State Circuits, vol. SC-20, No. 6, Dec. 1985 pp. 1158-1168.

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