Silicon-on-insulator H-transistor layout for gate arrays

Details Silicon-on-insulator H-transistor layout for gate arrays Silicon-on-insulator H-transistor layout for gate arrays

1992-08-17

1994-03-29

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

257202, 257347, 257401, H01L 2712, H01L 2710, H01L 2978

Patent

active

052987736

ABSTRACT:
A digital silicon-on-insulator (SOI) H-transistor layout is disclosed for gate arrays. In the preferred embodiment, the invention basically comprises at least two H-transistors; the ends of each H-transistor terminate in two distinct regions of field oxide; the two sides of the H-transistor abut a body contact region; and each body contact region abuts a strip of field oxide, which has an underlying trench. This pattern is repeated vertically and horizontally, generating a structure compatible for gate array architecture. In a gate array, all transistors in a column are of the same type, such as N type or P type. Within a row, however, the transistors types could alternate.

REFERENCES:
patent: 4513307 (1985-04-01), Brown
patent: 4602270 (1986-07-01), Finegold et al.
patent: 4791474 (1988-12-01), Sugiura
patent: 4899202 (1990-02-01), Blake et al.
patent: 4914491 (1990-04-01), Vu
patent: 5187113 (1993-02-01), Tyson et al.

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