Memory management unit for managing address operations correspon

Details Memory management unit for managing address operations correspon Memory management unit for managing address operations correspon

1994-09-26

1996-12-03

Chan, Eddie P.

395416, 395406, 395670, G06F 1210, G06F 934

Patent

active

055817220

ABSTRACT:
A memory management unit (MMU) for controlling a CPU's right to access a memory in order to initiate performance of an operation. The MMU includes a translator for translating a virtual address issued by the CPU into a physical address, a domain number and a permission, and an environment controller for determining if a portion of the memory corresponding to the domain number can be accessed by the CPU. The translator includes a translation look-aside buffer (TLB) for generating the physical address, the domain number and the permission, provided an entry in a translation table of the TLB matches a page number component of the virtual address. The translator also includes translation table look-up logic which supplies entry information to the translation table of the TLB by finding a match for the page number component in the memory if a match cannot be found in the TLB. The translator also includes permission control logic which evaluates the permission and either stops the operation or allows it to continue to be performed. The MMU also typically includes a manager which has the ability, primarily based on the domain number, to override the decisions of the permission control logic.

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