Patent
1995-05-15
1996-12-03
Downs, Robert W.
395 11, 395 24, 395 26, G06F 1518
Patent
active
055816622
ABSTRACT:
A hierarchical signal processing apparatus includes aggregates having logic operation portions. The apparatus compares a final output signal from a logic operation portion in a final aggregate with a teaching signal, and generates an error signal by taking a signal which exists only in the teaching signal as a positive error signal, and taking a signal which exists only in said final output signal as a negative error signal. An error signal generating portion in the apparatus generates a positive error signal of a logic operating portion within a certain aggregate which supplies one or more output signals thereof to said logic operation means of another aggregate based on one or more logic operations on the excitatory weight function signal of said weight function signal, the positive error signal, the inhibitory weight function signal of said weight function signal and the negative error signal, and also generates a negative error signal of said logic operation means within said certain aggregate which supplies one or more output signals thereof to said logic operation means of said other aggregate based on one or more logic operations on the inhibitory weight function signal of said weight function signal, the positive error signal of said other aggregate, the excitatory weight function signal of said weight function signal and the negative error signal.
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Ebi Yutaka
Eguchi Hirotoshi
Furukawa Tatsuya
Furuta Toshiyuki
Horiguchi Hiroyuki
Downs Robert W.
Katbab A.
Ricoh & Company, Ltd.
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