Integrated circuit memory having control circuitry for shared da

Details Integrated circuit memory having control circuitry for shared da Integrated circuit memory having control circuitry for shared da

1994-05-31

1996-05-28

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Sync/clocking

36523003, 36523006, G11C 800

Patent

active

055218806

ABSTRACT:
A memory system includes two memory arrays coupled to a global data bus via respective address decode circuits. Address control circuitry defaults to the weaker memory array upon receiving a new address such that the stronger memory array will not produce false values on the bus prior to stabilization of the address and proper decode. Consequently, the weaker memory array is not faced with a situation where it must overcome the previous false signal prior to developing the proper output values on the bus.

REFERENCES:
patent: 5247644 (1993-09-01), Johnson et al.
patent: 5270974 (1993-12-01), Reddy
patent: 5343427 (1994-08-01), Teruyama

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