Static information storage and retrieval – Floating gate – Particular biasing
Patent
1994-09-02
1996-05-28
Popek, Joseph A.
Static information storage and retrieval
Floating gate
Particular biasing
36518525, G11C 1606
Patent
active
055218660
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to electrically erasable non-volatile semiconductor memory devices (EEPROMs), and more particularly to a so-called flash memory that stores information in the form of electric charges accumulated in a floating gate.
2. Description of the Related Art
Recently, intensive efforts are being made on research and development of so-called flash memories. Flash memories, having a compact and solid construction, are expected to replace bulky and fragile conventional hard disk devices in various computers, including laptops. As each memory cell in the flash memory is formed of a single transistor similar to the memory cell transistor of conventional dynamic random access memories, flash memories can easily realize high integration density and large storage capacity. Further, flash memories have no movable parts such as driving motors, and consume little electric power.
In flash memories, each memory cell has a construction similar to a MOS transistor and includes a source region and a drain region formed in a semiconductor substrate. Further, there is provided a floating gate between the substrate and a control electrode such that the floating gate is insulated by a thin tunneling insulation film, wherein the control electrode corresponds to the gate electrode of conventional MOS transistors. When storing information, a predetermined control voltage is applied to the gate electrode. Thus, carriers flowing from the source region to the drain region are accelerated in the vicinity of the drain region and are injected into the floating gate through the aforementioned tunneling insulation film. The carriers, and hence the electric charges thus injected to the floating gate, are held therein stably and urge the potential level of the floating gate to a predetermined level. As a result, the flow of carriers from the source to the drain is controlled to on and off states by the carriers stored in the floating gate. In other words, it is possible to read the electric charges, and hence the information stored in the floating gate, by detecting the drain current of the memory cell transistor. When erasing information thus stored, a potential is applied to the control electrode such that the electric charges in the floating gate are expelled, simultaneously, to a potential that is applied to the semiconductor substrate or to the source region in the substrate for extracting the electric charges from the floating gate. As a result, the electric charges in the floating gate are dissipated, through the aforementioned tunneling insulation film, either to the semiconductor substrate or to the source region in the substrate.
FIG. 1 schematically shows the construction of the memory cell in the conventional flash memory described above.
Referring to FIG. 1, the memory cells are formed on a semiconductor substrate 10, which may be doped to the p-type for example, in an arrangement of rows and columns, wherein each of the memory cells includes an n.sup.+ -type source region 11a and an n.sup.+ -type drain region 11b on the substrate 10, spaced such that the regions 11a and 11b are separated from each other by a p-type channel region 10a interposed therebetween. The part of the semiconductor substrate 10 corresponding to the channel region 10a is covered by a tunneling insulation film 12a, and a floating gate electrode 12 is provided on the tunneling insulation film 12a. Further, the gate electrode 12 is covered by an interlayer insulation film 13a, and a control electrode 13 is provided on the interlayer insulation film 13a.
When storing information, a negative source voltage Vs is applied to the source region 11a, and a positive drain voltage Vd is applied to the drain region 11b, such that electrons flow from the source region 11a to the drain region 11b through the channel region 10a. Further, a positive control voltage Vg is applied to the control electrode 13. Thereby, the electrons flowing from the source region 11a to the drain region 1
REFERENCES:
patent: 4959812 (1990-09-01), Momodomi et al.
patent: 5265059 (1993-11-01), Wells et al.
patent: 5388078 (1995-02-01), Arakawa
Fujitsu Limited
Popek Joseph A.
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