Method for fabricating a field effect transistor

Details Method for fabricating a field effect transistor Method for fabricating a field effect transistor

1993-05-21

1994-03-29

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437133, 437184, 437912, 148DIG53, 148DIG106, 148DIG110, H01L 21265

Patent

active

052984451

ABSTRACT:
In a method for fabricating a FET of the present invention, first and second side walls are formed on a side surface of a gate electrode, and two n-GaAs layers are formed on an active layer by selective growth using the side walls as a mask. After that, the side walls are removed, whereby double recesses are formed around the gate electrode.

REFERENCES:
patent: 4632710 (1986-12-01), Van Rees
patent: 4711858 (1987-12-01), Harder et al.
patent: 4977100 (1990-12-01), Shimura
patent: 5182218 (1993-01-01), Fujihira
patent: 5196359 (1993-03-01), Shih et al.
Sonoda et al; "High-Efficiency and Highly Reliable 20W GaAs Power Field Effect Transistor in C Band"; Jpn. J. Appl. Phys. vol. 31 (8) part 1, Aug. 1992, pp. 2374-2381.
Macksey, "GaAs Power FET's Having the Gate recess Narrower than the Gate", IEEE Electron Letter, vol. EDL 7, No. 2, Feb. 1986, pp. 69-70.

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