Fishing – trapping – and vermin destroying
Patent
1991-12-26
1994-03-29
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
148DIG162, 365201, 437 48, H01L 2708, G11C 700
Patent
active
052984338
ABSTRACT:
A method for manufacturing semiconductor devices according to this invention, comprises the wafer manufacturing step of forming an integrated circuit with a redundant circuit in each of a plurality of chip areas on a semiconductor wafer and also forming at least one stress testing terminal that applies a stress testing voltage or stress testing signal to the interconnections other than those for power supply in the integrated circuit for each of the chip areas or for every certain number of the chip areas, the step of, after the wafer manufacturing step, screening failures by applying a specified stress testing control signal or stress voltage to a certain number of chip areas with the stress testing terminal in contact with a contact terminal of a tester in the wafer state, the step of, after the screening step, judging whether or not the electrical characteristics of each chip area are acceptable through die sort test, the step of remedying an integrated circuit in a chip area judged to be defective in the judging step, by means of the redundant circuit, and the assembly step of, after the remedying step, separating the chip areas into individual elements and then assembling them into an integrated circuit device.
REFERENCES:
patent: 4860260 (1989-08-01), Saito et al.
patent: 4866676 (1989-09-01), Crisp et al.
patent: 4999813 (1991-03-01), Ohtsuka et al.
patent: 5131018 (1992-07-01), McAdams et al.
patent: 5138427 (1992-08-01), Furuyama
Chaudhuri Olik
Horton Ken
Kabushiki Kaisha Toshiba
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