Multiplexed byte enable bus for partial word writes to ECC prote

Details Multiplexed byte enable bus for partial word writes to ECC prote Multiplexed byte enable bus for partial word writes to ECC prote

1992-06-30

1994-11-29

Baker, Stephen M.

Excavating

395425, G06F 1204, G06F 1110

Patent

active

053696514

ABSTRACT:
The present invention discloses a method and apparatus for minimizing the number of pins required in a memory system for support of partial word write operations to an ECC protected memory array. A memory system is provided having a memory controller which is coupled to a system bus via a first control bus and to an ECC protected memory array via a second control bus. The memory system also includes a data path buffer which is similarly connected to the system bus via a first data bus and to the memory array via a second data bus. Furthermore, a first control bus is coupled between the memory controller and the data path buffer. A byte enable bus is provided for transmitting eight byte enable signals therebetween. A multiplexor and a demultiplexor are arranged at the respective ends of the byte enable bus for multiplexing and demultiplexing the signals as they are transmitted. Upon transmission of the multiplexed signals from the memory controller to the data path buffer, the data bytes of a data string are merged with corresponding data bytes of a memory string to form a modified memory string. In the memory system of the present invention, only two (multiplexed) byte enable lines are required to transmit the eight byte enable signals required to perform the merge operation.

REFERENCES:
patent: 3573728 (1971-04-01), Kolankowski
patent: 4204634 (1980-05-01), Barsuhn
patent: 4520439 (1985-05-01), Liepa
patent: 5048022 (1991-09-01), Bissett et al.
patent: 5247644 (1993-09-01), Johnson et al.
patent: 5276832 (1994-01-01), Holman, Jr.

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