Microinstruction addressing in high-speed CPU

Details Microinstruction addressing in high-speed CPU Microinstruction addressing in high-speed CPU

1988-07-20

1991-06-11

Shaw, Gareth D.

Boots, shoes, and leggings

36424342, 3642477, 3642545, 3642443, 3642318, 3644336, 3649654, 3649576, 36494831, 3649397, G06F 924, G06F 922

Patent

active

050238280

ABSTRACT:
A memory stack used for storing microinstruction addresses in a pipelined CPU is constructed as a last-in, first-out memory using a stack pointer which applies a read control to one location of the stack and applies a write control to the next higher location. An unconditional read and write is done every machine cycle, before a microinstruction could be decoded, then the data on the read bus, or data from the write bus, is used and the pointer is incremented or decremented if a stack Push or Pop is decoded. These correspond to a Call or Return microinstruction. Thus the delay in decoding the microinstruction does not prevent completion of the stack operation in one machine cycle.

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Mishra, "The VAX 8800 Microarchitecture", Digital Technical Journal, Feb. 1987, pp. 20-33.
Troiani et al., "The VAX 8600 I Box, A Pipelined Implementation of the VAX Architecture", Digital Technical Journal, Aug. 1985, pp. 24-42.

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